Modern digital electronic devices often comprise a plurality of MOSFET. With the downscaling of the dimensions of the new transistors, negative bias temperature instability NBTI and hot carrier injection HCI degradations are becoming more important with respect to a long term reliability. It has become clear within recent years that degradation induced by NBTI and HCI will be present in most of the novel electronic devices. While NBTI is relevant for pMOSFETs, HCI is more relevant for nMOSFETs. The actual result of such a degradation will be a slowing down of the speed of digital circuitry. On the other hand, the threshold voltage and the saturated drain current may shift due to these degradations.
Although these degradations can be predicted e.g. by means of wafer-level reliability tests with a single isolated device during a process qualification phase, the detection and diagnosing of the aging effects of NBTI and HCI on VLSI circuitry is difficult, the operation of the circuits is not to be influenced. Furthermore, such a detection and diagnosis will require extra circuit blocks and therefore more circuit area.
Due to a typical slowing down of any degradated digital circuitry, the relative timing of data and clock signals may be altered and may cause timing violations. One way to avoid these timing violations is to increase the timing margins for the data and clock signals. However, such an increase of the timing margins will lead to a reduction of the chip performance in particular if pipelined circuits with speed critical parts are used. In addition, typically the optimal timing margin and the clock latencies are determined for given operating conditions and cannot be adjusted after the fabrication of the chips.